Alif Semiconductor /AE722F80F55D5LS_CM55_HE_View /I3C /I3C_DEVICE_CTRL

This bit is used in Master mode of operation. This bit is used to include I3C Broadcast address (0x7E) for private transfer. If I3C Broadcast address is not included for the private transfers, In-Band Interrupts (IBI) driven from slaves might not win address arbitration. Hence, the IBIs get delayed.

0 (Val_0x0): I3C Broadcast address is not included for Private Transfers

1 (Val_0x1): I3C Broadcast address is included for Private Transfers

This bit is used in Master mode of operation. This bit indicates whether any legacy I2C devices are present in the system.

0 (Val_0x0): I2C Slave not present

1 (Val_0x1): I2C Slave present

This bit is used in Master mode of operation. This bit acts as a global control to ACK/NACK the Hot-Join request from the devices. The I3C Master ACK/NACKs the Hot-Join request from other devices connected on the I3C bus, based on programming of this bit.

0 (Val_0x0): ACK Hot-Join requests

1 (Val_0x1): NACK and send broadcast CCC to disable Hot-Join

This bit is used in Slave mode of operation. After POR, the slave controller is enabled only after it sees both SDA and SCL lines IDLE for a specified time. This IDLE time is calculated by multipliying IDLE_CNT_MULITPLIER with the I3C_BUS_FREE_AVAIL_TIMING[BUS_AVAILABLE_TIME] field.

0 (Val_0x0): BUS_AVAILABLE_TIME x 1

1 (Val_0x1): BUS_AVAILABLE_TIME x 2

2 (Val_0x2): BUS_AVAILABLE_TIME x 4

3 (Val_0x3): BUS_AVAILABLE_TIME x 8

This field is used in Slave mode of operation. Note: When I2C mode strap is driven to 0x0, the slave controller operates in Adaptive mode. Setting of this bit is NOT required to put the controller in Adaptive mode. It is only used to enable some features of the slave controller to adapt to Adaptive I2C/I3C mode of operation. This bit is cleared automatically if the controller determines the mode as I3C. Effect on Hot-Join:

• If this bit is programmed to 0x1, the controller initiates a Hot-Join request only after it has switched to I3C mode of operation.
• If this bit is not set, the controller initiates a Hot-Join without determining the bus mode assuming itself to be on I3C bus.
• This bit should be set only if the slave application does not know to which bus the device is connected to.

This bit is used to enable or disable the DMA handshaking interface, and is applicable to both Master and Slave modes of operation.

0 (Val_0x0): The DMA handshake control has no significance.

1 (Val_0x1): Enables the DMA handshake control to interact with external DMA.

This bit is used in Master mode of operation and allows the controller to relinquish the I3C bus before completing the issued transfer. In response to an ABORT request, the controller issues the STOP condition after the complete data byte is transferred or received. This bit is auto-cleared once the transfer is aborted and the controller issues a I3C_INTR_STATUS[TRANSFER_ABORT_STS] bit.

This bit is used to resume the controller after it goes to the HALT state. In the Master mode of operation, the controller goes to the HALT state (as indicated in I3C_PRESENT_STATE[CM_TFR_ST_STS] field) due to any type of error in the transfer. The error type is specified in the response packet available in I3C_RESPONSE_QUEUE_PORT[RESPONSE] as per the value in ERR_STATUS field . After the controller gones to the HALT state, the application has to write 0x1 to this bit to resume the controller. This bit is auto-cleared once the controller resumes the transfers by initiating the next command. In the Slave mode of operation, the controller goes to the HALT state due to following conditions:

• Any type of error in the transfer
• I3C_SLV_MAX_LEN[MRL] field updated by the master through SETMRL CCC.

Controls whether or not I3C is enabled. In Master mode of operation, software can disable I3C while it is active. However, the controller may not get disabled immediately and it is disabled after commands in the Command queue are executed leading to a STOP condition on the bus and Master FSM is in IDLE state (as indicated by I3C_PRESENT_STATE register). In Slave mode of operation, software can disable I3C while it is active. However, the disable happens after the ongoing transfer is completed on the I3C bus. Software can read back 0x0 from this bit once disabling of I3C is completed. After POR, the I3C slave controller is enabled by programming this bit to 0x1. However, the I3C bus interface of the controller, responds to transfer on the bus only after it observes Bus Available condition for BUS_AVAILABLE_TIME x IDLE_CNT_MULTPLIER counts of PCLK period. The successful completion of enable/disable of the controller depends on availability of SCL to the controller at the time of performing this operation, and hence may not happen instantly.

0 (Val_0x0): Disables the I3C controller

1 (Val_0x1): Enables the I3C controller